Visit the Customer Training Center to access our library of training materials across a variety of subjects.
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| On-Demand Courses for Free |
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| Getting Started with the Versal ACAP Platform Introduces the Versal™ architecture and design methodology. This is a one-day version of the Designing with the Versal ACAP: Architecture and Methodology On-Demand course available for purchase. |
| Using Accelerated Applications with the Vision AI Starter Kit & System-on-Module (SOM) Learn about the Kria™ System-On-Module (SOM) and Vision AI Starter Kit, enabling you to accelerate applications using the Vision AI Starter Kit right out of the box without any installation or FPGA knowledge. |
| Using Accelerated Applications with the Kria KR260 Robotics Starter Kit Learn about the Kria SOM and Kria KR260 Robotics Starter Kit, enabling you to accelerate robotics-based applications using the KR260 Starter Kit right out of the box without any installation or FPGA knowledge. |
| Using Alveo Cards to Accelerate Dynamic Workloads An overview of the Alveo™ Data Center accelerator cards with an emphasis on learning on how to run a design on Alveo cards using the Vitis™ unified software platform. |
| On-Demand Courses for Purchase |
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| Accelerating Applications with the Vitis Unified Software Platform Learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis unified software environment targeting both data center (DC) and embedded applications. |
| Adaptive SoCs for System Architects Provides system architects with an overview of the capabilities and support for the Zynq™ UltraScale™ MPSoC and Versal devices. |
| Design Closure Techniques Learn how to achieve design closure more efficiently and productively by using the three pillars of design closure (functional closure, timing closure, and power closure). |
| Designing FPGAs Using the Vivado Design Suite 1 This course offers introductory training on the Vivado Design Suite and demonstrates the FPGA design flow for those uninitiated to FPGA design. |
| Designing FPGAs Using the Vivado Design Suite 2 Learn how to build a more effective FPGA design. This course builds on the concepts from the Designing FPGAs Using the Vivado Design Suite 1 course. |
| Designing FPGAs Using the Vivado Design Suite 3 Learn how to effectively employ timing closure techniques. This course builds on the concepts from the previous Designing FPGAs Using the Vivado Design Suite courses. |
| Designing FPGAs Using the Vivado Design Suite 4 Learn how to use the advanced aspects of the Vivado Design Suite and AMD hardware. This course buildes on the concepts from the previous Designing FPGAs Using the Vivado Design Suite courses. |
| Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite Learn how to construct, implement, and download a Dynamic Function eXchange (DFX) FPGA design using the Vivado Design Suite. |
| Designing with the IP Integrator Tool Explore the IP integrator tool and its features to gain the expertise needed to develop, implement, and debug different IPI block designs using the Vivado Design Suite. |
| Designing with the UltraScale and UltraScale+ Architectures Introduces the UltraScale™ and UltraScale+™ architectures to both new and experienced designers. |
| Designing with the Versal ACAP: Architecture and Methodology Learn about Versal architecture and design methodology. |
| Designing with the Versal ACAP: Network on Chip Introduces the Versal network on chip (NoC) to users familiar with other SoC architectures. |
| Designing with the Versal ACAP: PCI Express Introduces the features and capabilities of the PCIe® and Cache Coherent Interconnect blocks in the Versal architecture. |
| Designing with the Versal ACAP: Power and Board Design Provides a system-level understanding of power and thermal issues related to designing with the Versal adaptive SoC |
| Designing with the Versal ACAP: Serial Transceivers Provides a system-level understanding of Versal device serial transceivers. |
| Designing with the Zynq UltraScale+ RFSoC This course provides an overview of the hard block capabilities for the Zynq UltraScale+ RFSoC family with a special emphasis on the Data Converter and Soft-Decision FEC blocks. |
| Designing with Verilog Provides a thorough introduction to the Verilog language. |
| Designing with Versal AI Engine: Architecture and Design Flow - 1 This course describes the Versal AI Engine architecture, how to program the AI Engine, the data communications between the PL and AI Engines, how to analyze the kernel program using various debugger features. |
| Designing with Versal AI Engine: Graph Programming with AI Engine Kernels - 2 Describes the system design flow and interfaces that can be used for data movements in the Versal AI Engine. |
| Designing with Versal AI Engine 3: Kernel Programming and Optimization - 3 Covers the advanced features of the Versal AI Engine, including debugging an application in the Vitis unified software environment, using filter intrinsics, implementing a system design in hardware, and optimizing an AI Engine kernel program. |
| Designing with VHDL Provides a thorough introduction to the VHDL language. |
| Developing AI Inference Solutions with the Vitis AI Platform This course describes how to use the Vitis AI development platform in conjunction with DNN algorithms, models, inference and training, and frameworks on cloud and edge computing platforms. |
| Developing Multimedia Solutions with the Video Codec Unit Using the GStreamer Framework Learn how to build and run complex multimedia applications targeting Zynq UltraScale+ MPSoC EV devices with the help of the GStreamer framework. |
| Embedded Design with PetaLinux Tools This course provides embedded systems developers experience with creating an embedded Linux system targeting AMD SoCs using the PetaLinux tools. |
| Embedded Systems Design Highlights the general embedded concepts, tools, and techniques using the Vivado Design Suite. |
| Embedded Systems Software Design This course introduces the concepts, tools, and techniques required for software design and development. |
| High-Level Synthesis with the Vitis HLS Tool This course provides a thorough introduction to the Vitis High-Level Synthesis (HLS) tool. |
| Migrating to the Vitis Embedded Software Development IDE Workshop This workshop demonstrates the tools and techniques required for software design and development using the Vitis unified software platform. |
| Operating Systems and Hypervisors in Adaptive SoCs Provides software developers options and techniques for selecting and implementing various types of operating systems and hypervisors on Zynq UltraScale+ MPSoC and Versal devices. |
| UltraFast Design Methodology Learn how to improve design speed and reliability by using theUltraFast Design Methodology and the Vivado Design Suite. |
| Using Vision-based Applications with the Kria KV260 Vision AI Starter Kit and System-on-Module Learn about the Kria System-on-Module (SOM) and Kria KV260 Vision AI Starter Kit, enabling you to accelerate vision based applications using the KV260 Starter Kit right out of the box. |
| Vitis Model Composer: A MATLAB and Simulink-based Product Provides experience with using the Vitis Model Composer tool for model-based designs. |
| Zynq UltraScale+ MPSoC: Boot and Platform Management Provides software developers responsible for booting and platform management with an overview of the capabilities and support for the Zynq UltraScale+ MPSoC. |
| Zynq UltraScale+ MPSoC for the Hardware Designer This course provides hardware designers with an overview of the capabilities and support for the Zynq UltraScale+ MPSoC family from a hardware architectural perspective. |