Memory Interfaces Design Hub - UltraScale DDR3/DDR4 Memory
This page covers Memory Interfacing in UltraScale Devices using the Memory Interface Generator (MIG) in the Vivado Design Suite
Additional Learning Materials
| User Guides | Date |
|---|---|
 UG583 - UltraScale Architecture PCB Design Guide | 07/27/2022 |
| UG571 - UltraScale Architecture SelectIO Resources User Guide | 09/01/2022 |
| UG572 - UltraScale Architecture Clocking Resources User Guide | 08/25/2021 |
| Vivado Design Hubs | Date |
 DH0007 - I/O and Clock Planning | |
| DH0003 - Designing with IP | |
| DH0009 - Using IP Integrator | |
| Memory Interface Design Tips | Date |
| PG150 - Migrating Memory IP Using Vivado | 04/20/2022 |
| UG583 - PCB Trace Derating | 07/27/2022 |
| PG150 - Using the Memory IP Traffic Generator | 04/20/2022 |
| Targeted Reference Designs | Date |
| DH0043 - Kintex UltraScale FPGA KCU105 Evaluation Kit |
Support Resources
Please visit the Xilinx Service Portal to open or review a service request.
