Getting Started | Design Resources | Support Resources | Transceiver IP Resources |
Refer to the High Speed Serial Product Page for more information on Xilinx GTY Transceivers.
High-Speed Serial I/O Designer's Guide | Date |
---|---|
Basic Concepts | |
Purpose of SERDES | |
History of SERDES | |
Alignment, Encoding, Emphasis, Buffers, Channel Bonding and Clock Correction | |
UltraScale GTY Transceivers User Guide | Date |
UG578 - RX Byte and Word Alignment | 09/14/2021 |
UG578 - RX 8B/10B Decoder | 09/14/2021 |
UG578 - Buffer Control | 09/14/2021 |
UG578 - RX Clock Correction | 09/14/2021 |
UG578 - RX Channel Bonding | 09/14/2021 |
UG578 - RX Synchronous Gearbox | 09/14/2021 |
UG578 - RX Clock Data Recovery (CDR) | 09/14/2021 |
The characterization reports for UltraScale and UltraScale+ devices are confidential. Please contact a Xilinx Specialist for more information.
Supported Protocols | Date |
---|---|
DS923 - Virtex UltraScale+ - GTY Transceiver Protocol List | 06/23/2021 |
DS922 - Kintex UltraScale+ - GTY Transceiver Protocol List | 02/16/2021 |
DS893 - Virtex UltraScale - GTY Transceiver Protocol List | 05/23/2019 |
DS892 - Kintex UltraScale - GTY Transceiver Protocol List | 09/22/2020 |
Max Data Rates | Date |
DS923 - Virtex UltraScale+ - GTY Transceiver Performance | 06/23/2021 |
DS922 - Kintex UltraScale+ - GTY Transceiver Performance | 02/16/2021 |
DS893 - Virtex UltraScale - GTY Transceiver Performance | 05/23/2019 |
DS892 - Kintex UltraScale - GTY Transceiver Performance | 09/22/2020 |
Refer to the UltraScale FPGAs Transceivers Wizard IP Product Page for more information regarding this IP.
Using the Wizard IP Core | Date |
---|---|
PG182 - Overview | 12/04/2020 |
PG182 - Designing with the Core | 12/04/2020 |
PG182 - Design Flow Steps | 12/04/2020 |
PG182 - Example Design | 12/04/2020 |
PG182 - Test Bench Usage | 12/04/2020 |
AR70679 - UltraScale Transceiver Wizard - Release Notes and Known Issues |
Determining Latency | Date |
---|---|
AR69011 - UltraScale+ GTY Transceiver - TX and RX Latency Values | |
AR66341 - UltraScale GTY Transceiver - TX and RX Latency Values | |
Rate Changing | Date |
AR70485 - UltraScale+ GTH/GTY Transceivers - How to Update CPLL Calibration Settings During a Rate Change | |
Frequently Asked Questions (FAQ) | Date |
AR64440 - UltraScale GTY Transceiver - Known Issues and Answer Record List |