Versal Prime Series
The Versal Prime series provides a diverse set of compute engines, next-generation I/O, and integrated DDR controllers, enabling low latency acceleration across a wide range of workloads.
Optimized for Connectivity, Inline Acceleration, and Diverse Workloads
Scalar Engines
Three scalar processor types are available in Versal™ adaptive SoCs to support diverse application needs. The application processing unit is ideal for complex applications supported by an OS, and the real-time processing unit is ideal for applications which need low latency, determinism, and real-time control. A separate platform management controller manages system boot, security, and debug.
Adaptable Engines
Programmable logic enables the development of custom computational blocks for ever-changing algorithms. The rearchitected logic in Versal adaptive SoCs provides 4X density per CLB, reducing the need for costly global routing. Loaded with a wide variety of memory elements and tightly coupled with programmable I/O, the adaptable engines allow users to create powerful accelerators for any application.
Intelligent Engines
Enhanced DSP engines provide support for new operations and data types, including single and half-precision floating point and complex 18x18 operations. With backwards compatibility to UltraScale+™ designs, users can continue to leverage existing libraries and IP or update their designs to capture the improved compute performance enabled by this new architecture.
Next-Generation I/O
The Versal Prime series combines PCIe® Gen4/Gen5 compliance, CCIX support, high performance GPIO, and multirate Ethernet MACs supporting various ethernet configurations to maximize connectivity and flexibility. Additionally, Versal Prime series devices feature rearchitected low latency 32.75Gb/s transceivers, and certain devices support 58Gb/s PAM4 transceivers.
Integrated DDR Memory Controllers
Each integrated DDR memory controller provides up to 34.1GB/s of bandwidth with DDR4 and LPDDR4 support and is optimized for both linear and random traffic. In combination with the programmable Network on Chip, these integrated controllers eliminate the need for soft implementations in the programmable logic, saving development time and logic resources.
Programmable Network on Chip
The programmable network on chip (NoC) provides an optimized multi-terabit interconnect between the different compute engines and integrated IP blocks present in the Versal adaptive SoC architecture, simplifying timing closure and saving logic resources. The NoC compiler provides a streamlined programming experience while allowing users to manage latency and QoS, ensuring that critical data paths are prioritized.
Learn more about Industry Leading Transceiver Technology by AMD
High-speed serialGet started with the Versal Prime series VMK180 evaluation kit
Boards & KitsContact AMD sales representatives for more information
Contact SalesVersal Prime series solves a broad range of industry-specific problems with performance and flexibility
Storage Acceleration
With the dawn of AI and the explosion of data generated by modern applications, traditional compute has become an increasingly precious resource in the data center. One solution to preserve compute is to add accelerators to storage controllers and endpoints to offload compression and other common tasks from the primary processor. The Versal™ Prime series combines PCIe® Gen4/Gen5 support, powerful Arm® scalar processing engines, integrated memory controllers, and next-generation programmable logic to reduce system-level bottlenecks and increase efficiency.
Data Center Network Acceleration
FPGAs and SoCs have long played a key role in accelerating data center applications by offloading common networking functions such as encryption/decryption and virtual switching from the central processor in a system, preserving compute cycles. Versal adaptive SoCs further accelerate data center systems by combining PCIe Gen4/Gen5 support, next-generation SerDes, and a multirate Ethernet MAC with powerful heterogeneous compute engines to both offload networking operations and supplement the compute available in a server with additional inline processing.
5G xHaul
As 5G is emerging, the demand for high-bandwidth connectivity requires access networks to adapt to support new protocols, such as eCPRI, while still maintaining compatibility with existing standards. The combination of adaptable engines with industry-leading SerDes and Ethernet technology in the Versal Prime series gives operators the processing power needed to handle 5G throughput requirements while maintaining legacy standard support and reducing total cost of ownership.
Passive Optical Networks
As competition from wireless services increases, cable broadband providers must scale their networks and deliver higher bandwidth service to remain competitive. The Versal Prime series offers twice the programmable logic as existing MPSoC devices, powerful Arm scalar processing engines, greater SerDes density, integrated Ethernet IP blocks, and thermally optimized packaging to enable low power, efficient designs without compromising performance.
Communications Test Equipment
The massive explosion in bandwidth that accompanies the latest communications standards makes it challenging for test equipment vendors to keep pace with market demands. With support for 58G transceivers and multirate Ethernet MACs, the Versal Prime series offers high-performance data handling and analysis for wired communication testers. The programmable NoC and integrated memory controllers enable fast and efficient data movement for complex test algorithms.
Versal™ Prime Series Features Overview
Scalar Engines Features
| VM1102 | VM1302 | VM1402 | VM1502 | VM1802 | VM2202 | VM2302 | VM2502 | VM2902 | |
|---|---|---|---|---|---|---|---|---|---|
| Application Processing Unit | Dual-core Arm® Cortex®-A72, 48KB/32KB L1 Cache w/ parity & ECC; 1MB L2 Cache w/ ECC | ||||||||
| Real-time Processing Unit | Dual-core Arm Cortex-R5F, 32KB/32KB L1 Cache, and 256KB TCM w/ECC | ||||||||
| Memory | 256KB On-Chip Memory w/ECC | ||||||||
| Connectivity | Ethernet (x2); USB 2.0 (x1); UART (x2); SPI (x2); I2C (x2); CAN-FD (x2) | ||||||||
Intelligent Engines Features
| VM1102 | VM1302 | VM1402 | VM1502 | VM1802 | VM2202 | VM2302 | VM2502 | VM2902 | |
|---|---|---|---|---|---|---|---|---|---|
| DSP Engines | 464 | 832 | 1,696 | 1,312 | 1,968 | 1,312 | 1,904 |
3,984 | 2,672 |
Adaptable Engines Features
| VM1102 | VM1302 | VM1402 | VM1502 | VM1802 | VM2202 | VM2302 | VM2502 | VM2902 | |
|---|---|---|---|---|---|---|---|---|---|
| System Logic Cells (K) | 329 | 693 | 1,238 | 981 |
1,968 | 1,139 | 1,575 | 1,969 | 2,233 |
| LUTs | 150,272 | 316,928 | 565,760 | 448,512 |
899,840 | 520,704 | 719,872 | 900,224 | 1,020,928 |
Foundational Platform Features
| VM1102 | VM1302 | VM1402 | VM1502 | VM1802 | VM2202 | VM2302 | VM2502 | VM2902 | |
|---|---|---|---|---|---|---|---|---|---|
| NoC Master / NoC Slave Ports | 5 | 9 | 18 | 21 |
28 | 21 | 30 | 28 |
42 |
| DDR Memory Controllers | 1 | 2 | 4 | 3 |
4 | 3 | 3 |
4 |
3 |
| CCIX & PCIe® w/ DMA (CPM) | - | 1 x Gen4x16, CCIX | 1 x Gen4x16, CCIX | 1 x Gen4x16, CCIX | 1 x Gen4x16, CCIX | 2 x Gen5x8, CCIX | - |
2 x Gen5x8, CCIX | - |
| PCIe | 1 x Gen4x8 | 2 x Gen4x8 | 2 x Gen4x8 | 4 x Gen4x8 | 4 x Gen4x8 | 4 x Gen5x4 | 2 x Gen5x4 | 2 x Gen5x4 | 2 x Gen5x4 |
| 100G Multirate Ethernet MAC | 1 | 2 | 2 | 4 | 4 | 2 | 6 | 2 | 6 |
| GTY Transceivers | 0 | 24 | 24 | 44 | 44 | 0 | 0 | 0 | 0 |
| GTYP Transceivers | 8 |
0 | 0 | 0 | 0 | 32 | 8 |
16 |
8 |
| GTM Transceivers | 0 |
0 |
0 |
0 |
0 |
0 | 40 | 0 | 40 |
Documentation
Versal Design Guidance and Documentation
AMD provides a breadth of documentation, resources, and methodologies to accelerate your development on the Versal™ architecture. If you’re not sure where to begin with Versal adaptive SoCs, the Design Flow Assistant is an interactive guide to help you create a development strategy, while the Design Process Hubs are a visual and streamlined reference to all Versal documentation by design process.
Search Documentation
Integrated Software and Hardware Platform for All Developers
With an inherently software programmable silicon infrastructure, the Versal™ adaptive SoC is designed from the ground up to be software-centric. The enhanced AMD Vivado™ ML Editions introduces a new system design methodology and development environments such as traffic analyzer, NoC compiler, data flow modeling, and more. A high-speed, unified, cohesive debug environment accelerates debug and trace across Scalar, Adaptable, and Intelligent engines.
Download Vivado ML Editions >
The AMD Vitis™ unified software platform provides comprehensive core development kits, libraries that use hardware-acceleration technology. The platform provides an efficient, convenient, and unified software environment from the cloud to the edge. As a proud member of the open source community, the Vitis unified software platform is entirely free and open source.
Download Vitis Unified Software Platform >
Versal Adaptive SoC Evaluation Kits
Be the first to experience the Versal adaptive SoC architecture, built from the ground-up to be natively software programmable. Through a host of tools, software, libraries, IP, middleware, and frameworks, adaptive SoCs enable dynamically customizable accelerated computing solutions through industry-standard design flows. The Versal Prime series VMK180 evaluation kit has everything you need to jump-start your designs.
Learn more about the Versal Prime series VMK180 evaluation kit >
Training Courses
AMD training and learning resources provide the practical skills and fundamental knowledge you need to be fully productive in your next development project.
Designing with the Versal ACAP: Architecture and Methodology
Designing with the Versal ACAP: Network on Chip
Designing with the Versal ACAP: Power and Board Design
Versal Design Guidance and Documentation
AMD provides a breadth of documentation, resources, and methodologies to accelerate your development on the Versal™ architecture. If you’re not sure where to begin with Versal adaptive SoCs, the Design Flow Assistant is an interactive guide to help you create a development strategy, while the Design Process Hubs are a visual and streamlined reference to all Versal documentation by design process.
