• A comprehensive core development kit to seamlessly build accelerated applications
• A rich set of hardware-accelerated open-source libraries optimized for AMD FPGA and Versal™ adaptive SoC hardware platforms
• Plug-in domain-specific development environments enabling development directly in familiar, higher-level frameworks
• A growing ecosystem of hardware-accelerated partner libraries and pre-built applications
• Vitis Model Composer, a model-based design tool that enables rapid design exploration and verification within the MathWorks MATLAB® and Simulink® environment and accelerates the path to production on AMD devices. 
• Vitis Networking P4, which allows for the creation of soft-defined networks. The VitisNetP4 data plane builder generates systems that can be programmed for a wide range of packet processing functions - from simple packet classification to complex packet editing.

Development in the Vitis environment enables portability from platform to platform, whether you are porting from a proof of concept, a development kit, or a custom board.

The Vitis platform-based design methodology provides many productivity advantages:

• Platform reuse: Swap different acceleration applications with the same platform
• Application portability: Port applications across different platforms with minimum effort
• Simulation time: Speed up co-simulation with kernels
• Run time: Open-source run time that takes care of host-device communication through a PCIe® or an embedded interface
• System debug: Save full hardware compile by co-simulating the full system

The Vitis AI development environment is a specialized development environment for accelerating AI inference on AMD embedded platforms, Alveo accelerator cards, or on the FPGA-instances in the cloud. Vitis AI development environment supports the leading deep learning frameworks like Tensorflow and Caffe, and offers comprehensive APIs to prune, quantize, optimize, and compile your trained networks to help achieve the highest AI inference performance for your deployed application. 

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Open-source, performance-optimized libraries that offer out-of-the-box acceleration with minimal to zero-code changes to your existing applications, written in C, C++ or Python. Leverage the domain-specific accelerated libraries as-is, modify to suit your requirements or use as algorithmic building blocks in your custom accelerators.

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A complete set of graphical and command-line developer tools that include the Vitis compilers, analyzers, and debuggers to build applications, analyze performance bottlenecks, and debug accelerated algorithms, developed in C, C++, or OpenCL™ APIs. Leverage these features within your own IDEs or use the standalone Vitis IDE.

The Xilinx Runtime library (XRT) facilitates communication between your application code (running on an embedded Arm or x86 host) and the accelerators deployed on the reconfigurable portion of PCIe® interface-based AMD accelerator cards, MPSoC-based embedded platforms, or adaptive SoCs. It includes user-space libraries and APIs, kernel drivers, board utilities, and firmware. 

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The Vitis target platform defines base hardware and software architecture and application context for AMD platforms, including external memory interfaces, custom input/output interfaces, and software runtime.

•For AMD accelerator cards on premises or in the cloud, the Vitis target platform automatically configures the PCIe interfaces that connect and manage communication between your FPGA accelerators and x86 application code—you don’t need to implement any connection details!

•For AMD embedded devices, the Vitis target platform also includes the operating system for the processor on the platform, boot loader and drivers for platform peripherals, and root file system. You can use predefined Vitis target platforms for AMD evaluation boards or define your own in the Vivado™ Design Suite.

Vitis Model Composer is an AMD toolbox for the MATLAB and Simulink environment that enables rapid design exploration and verification within the MATLAB and Simulink tool and accelerates the path to production on AMD devices.

• Create a design using optimized blocks targeting AI Engines and programmable logic. Visualize and analyze simulation results and compare the output to golden references generated using the MATLAB and Simulink software.
• Seamlessly co-simulate AI Engine and programmable logic (HLS, HDL) blocks. 
• Automatically generate code (AI Engine dataflow graphs, RTL, HLS C++) and test benches for a design. 
• Validate your design in hardware with ease of use.

The Vitis™ HLS tool allows users to easily create complex FPGA algorithms by synthesizing a C/C++ function into RTL. The Vitis HLS tool is tightly integrated with both the Vivado™ Design Suite for synthesis and place & route and the Vitis™ unified software platform for heterogenous system designs and applications.

• Using the Vitis HLS flow, users can apply directives to the C code to create the RTL specific to a desired implementation.
• Multiple design architectures can be created from the C source code and a path for high-quality, correct-by-construction RTL is enabled.
• C simulation can be used to validate the design and allows faster iterations than a traditional RTL-based simulation. 
• The Vitis HLS tool features a rich set of analysis and debugging tools that facilitate design optimization.